Abdullah Giray Yağlıkçı
Incoming Faculty at Helmholtz Center for Information Security (CISPA)
Education
Co-Supervised Publications
Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance in HPCA 2025
We 1) present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting (PRAC) and 2) propose Chronus, a new mechanism that addresses PRAC's two major weaknesses. Our analysis shows that PRAC's system performance overhead on benign applications is non-negligible for modern DRAM chips and prohibitively large for future DRAM chips that are more vulnerable to read disturbance. We identify two weaknesses of PRAC that cause these overheads. First, PRAC increases critical DRAM access latency parameters due to the additional time required to increment activation counters. Second, PRAC performs a constant number of preventive refreshes at a time, making it vulnerable to an adversarial access pattern, known as the wave attack, and consequently requiring it to be configured for significantly smaller activation thresholds. To address PRAC's two weaknesses, we propose a new on-DRAM-die RowHammer mitigation mechanism, Chronus. Chronus 1) updates row activation counters concurrently while serving accesses by separating counters from the data and 2) prevents the wave attack by dynamically controlling the number of preventive refreshes performed. Our performance analysis shows that Chronus's system performance overhead is near-zero for modern DRAM chips and very low for future DRAM chips. Chronus outperforms three variants of PRAC and three other state-of-the-art read disturbance solutions. We discuss Chronus's and PRAC's implications for future systems and foreshadow future research directions. To aid future research, we open-source our Chronus implementation and the tools we develop to analyze PRAC.
BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads in MICRO 2024
In this work, we tackle the performance overheads of RowHammer solutions by tracking and throttling the generators of memory accesses that trigger RowHammer solutions. To this end, we propose BreakHammer. BreakHammer 1) observes the time-consuming RowHammer-preventive actions of existing RowHammer mitigation mechanisms, 2) identifies hardware threads that trigger many of these actions, and 3) reduces the memory bandwidth usage of each identified thread. As such, BreakHammer significantly reduces the number of RowHammer-preventive actions performed, thereby improving 1) system performance and DRAM energy, and 2) reducing the maximum slowdown induced on a benign application, with near-zero area overhead. Our extensive evaluations demonstrate that BreakHammer effectively reduces the negative performance, energy, and fairness effects of eight RowHammer mitigation mechanisms. To foster further research we open-source our BreakHammer implementation and scripts
Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions in HPCA 2025
In this paper, our goal is to mitigate RowHammer at low cost by understanding the impact of reduced preventive refresh latency on RowHammer. To this end, we present the first rigorous experimental study on the interactions between refresh latency and RowHammer characteristics in real DRAM chips. Our experimental characterization using 388 real DDR4 DRAM chips from three major manufacturers demonstrates that a preventive refresh latency can be significantly reduced (by 64%). To investigate the impact of reduced preventive refresh latency on system performance and energy efficiency, we reduce the preventive refresh latency and adjust the aggressiveness of existing RowHammer solutions by developing a new mechanism, Partial Charge Restoration for Aggressive Mitigation (PaCRAM). Our results show that PaCRAM reduces the performance and energy overheads induced by five state-of-the-art RowHammer mitigation mechanisms with small additional area overhead. Thus, PaCRAM introduces a novel perspective into addressing RowHammer vulnerability at low cost by leveraging our experimental observations. To aid future research, we open-source our PaCRAM implementation.
First-Author Publications
Enabling Efficient and Scalable DRAM Read Disturbance Mitigation via New Experimental Insights into Modern DRAM Chips in PhD Thesis, ETH Zürich, 2024
This PhD dissertation, based on my PhD research, demonstrates that we can mitigate DRAM read disturbance efficiently and scalably by 1) building a detailed understanding of DRAM read disturbance, 2) leveraging insights into modern DRAM chips and memory controllers, and 3) devising novel solutions that do not require proprietary knowledge of DRAM chip internals. This thesis comprehensively explains the cutting edge in DRAM read disturbance research as of August, 2024, and identifies future research avenues to address the outstanding and emerging challenges in the field.
Spatial Variation-Aware Read Disturbance Defenses in HPCA 2024
We tackle the performance overhead of existing read disturbance solutions by leveraging the spatial variation in read disturbance across different memory locations in real DRAM chips. To do so, we 1) present the first rigorous real DRAM chip characterization study of spatial variation of read disturbance and 2) propose Svärd, a new mechanism that dynamically adapts the aggressiveness of existing solutions based on the row-level read disturbance profile. Our experimental characterization on 144 real DDR4 DRAM chips representing 10 chip designs demonstrates a large variation in read disturbance vulnerability across different memory locations: in the part of memory with the worst read disturbance vulnerability, 1) up to 2x the number of bitflips can occur and 2) bitflips can occur at an order of magnitude fewer accesses, compared to the memory locations with the least vulnerability to read disturbance. Svärd leverages this variation to reduce the overheads of five state-of-the-art read disturbance solutions, and thus significantly increases system performance.
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips in MICRO 2022
We propose a new operation, Hidden Row Activation (HiRA), and the HiRA Memory Controller (HiRA-MC) to perform HiRA operations. HiRA hides a refresh operation's latency by refreshing a row concurrently with accessing or refreshing another row within the same bank. Unlike prior works, HiRA achieves this parallelism without any modifications to off-the-shelf DRAM chips. To do so, it leverages the new observation that two rows in the same bank can be activated without data loss if the rows are connected to different charge restoration circuitry. HiRA reduces the time spent on refresh operations by 51.4%. HiRA-MC increases system performance by 12.6% and 3.73× as it reduces the performance degradation due to periodic refreshes and refreshes for RowHammer protection (preventive refreshes), respectively, for future DRAM chips with increased density and RowHammer vulnerability.
Understanding RowHammer Under Reduced Wordline Voltage in DSN 2022
This is the first work to experimentally demonstrate on 272 real DRAM chips that lowering VPP reduces a DRAM chip's RowHammer vulnerability. We show that lowering VPP 1) increases the number of activate-precharge cycles needed to induce a RowHammer bit flip by up to 85.8 % with an average of 7.4 % across all tested chips and 2) decreases the RowHammer bit error rate by up to 66.9 % with an average of 15.2 % across all tested chips. At the same time, reducing VPP marginally worsens a DRAM cell's access latency, charge restoration, and data retention time within the guardbands of system-level nominal timing parameters for 208 out of 272 tested chips. We conclude that reducing VPP is a promising strategy for reducing a DRAM chip's RowHammer vulnerability without requiring modifications to DRAM chips.
A Deeper Look into RowHammer in MICRO 2021
We present an experimental characterization using 248 DDR4 and 24 DDR3 modern DRAM chips from four major DRAM manufacturers demonstrating how the RowHammer effects vary with three fundamental properties: 1) DRAM chip temperature, 2) aggressor row active time, and 3) victim DRAM cell's physical location. Among our 16 new observations, we highlight that a RowHammer bit flip 1) is very likely to occur in a bounded range, specific to each DRAM cell (e.g., 5.4% of the vulnerable DRAM cells exhibit errors in the range 70 °C to 90 °C), 2) is more likely to occur if the aggressor row is active for longer time (e.g., RowHammer vulnerability increases by 36% if we keep a DRAM row active for 15 column accesses), and 3) is more likely to occur in certain physical regions of the DRAM module under attack (e.g., 5% of the rows are 2x more vulnerable than the remaining 95% of the rows). Our study has important practical implications on future RowHammer attacks and defenses. We describe and analyze the implications of our new findings by proposing three future RowHammer attack and six future RowHammer defense improvements.
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows in HPCA 2021
In this paper, we show that it is possible to efficiently and scalably prevent RowHammer bitflips without knowledge of or modification to DRAM internals. We introduce BlockHammer, a low-cost, effective, and easy-to-adopt RowHammer mitigation mechanism that prevents all RowHammer bitflips while overcoming the two key challenges: scalability with worsening RowHammer vulnerability and compatibility with commodity DRAM chips. BlockHammer selectively throttles memory accesses that may cause RowHammer bitflips. To our knowledge, this is the first work that prevents RowHammer bitflips efficiently and scalably without knowledge of or modifications to DRAM internals.
Awards & Honors
- W. C. Carter PhD Dissertation Award in Dependability, 2025 - Recipient
- ACM SIGARCH / IEEE CS TCCA Outstanding Dissertation Award, 2025 - Honorable Mention
- ETH Medal, 2024 - Nominated
- HOST PhD Dissertation Competition, 2024 - Finalist
- IEEE TTTC E. J. McCluskey Best Doctoral Thesis Award, 2025 - Semi-finalist
- ACM PACT Student Research Competition, 2023 - Recipient for an early version of Svärd (HPCA 2024)
- Intel Hardware Security Academic Award, 2022 - Finalist for BlockHammer (HPCA 2021)
- ISCA Hall of Fame, 2025 - Inducted with 8 papers
- HPCA Hall of Fame, 2025 - Inducted with 10 papers
Selected Talks and Lectures
Lecture in EFCL Summer School
Memory Latency, Data Retention, and Refresh
90 mins |
Video: |
Slides:
Lecture in ETH Zurich
DRAM Robustness and RowHammer Lecture (Second half of the lecture)
1 hour |
Video: |
Slides:
SAFARI Live Seminar
A Deeper Look into RowHammer's Characteristics in Real Modern DRAM Chips
1 hour 50 mins |
Video: |
Slides:
SAFARI Live Seminar
Efficiently and Scalably Mitigating RowHammer in DRAM-Based Memory Systems
2 hours 4 mins |
Video: |
Slides:
Employment
Service
Student Assistant to PC chairs for DSN
Reviewer for DSN
Reviewer for TODAES
Subreviewer for ASPLOS, DSN, ISCA, CAL, DRAMSec, TC, TCAD, and USENIX ATC
Subreviewer for HPCA, MICRO, TCAD, and USENIX ATC
Subreviewer for DSN, ISCA, MICRO, CCS, ISCAS, ISPASS, NVMW, and TCSI
Subreviewer for DSN, ISCA, MICRO, MSST, TCAD, and TED
Subreviewer for ASPLOS, HPCA, PACT, Nature Electronics, TC, and TVLSI
Subreviewer for DSN, MICRO, ISCA, and PLDI
Other Publications
MIMDRAM [HPCA, 2024]
pim
pum
mimd
dram
Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikçi, F. Nisa Bostanci, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu, "MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing" Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA), Edinburgh, UK, March 2024. Full Paper: Extended Version: Source Code:
Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikçi, F. Nisa Bostanci, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu, "MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing" Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA), Edinburgh, UK, March 2024. Full Paper: Extended Version: Source Code:
RowPress [ISCA, 2023]
rowhammer
read disturbance
rowpress
dram
mitigation
attack
Haocong Luo, Ataberk Olgun, A. Giray Yaglikci, Yahya Can Tugrul, Steve Rhyner, M. Banu Cavlak, Joel Lindegger, Mohammad Sadrosadati, and Onur Mutlu, "RowPress: Amplifying Read Disturbance in Modern DRAM Chips" Proceedings of the 50th International Symposium on Computer Architecture (ISCA), Orlando, FL, USA, June 2023. Full Paper: Extended Version: Lightning Talk (3 mins): Full Talk (26 mins): Source Code:
Haocong Luo, Ataberk Olgun, A. Giray Yaglikci, Yahya Can Tugrul, Steve Rhyner, M. Banu Cavlak, Joel Lindegger, Mohammad Sadrosadati, and Onur Mutlu, "RowPress: Amplifying Read Disturbance in Modern DRAM Chips" Proceedings of the 50th International Symposium on Computer Architecture (ISCA), Orlando, FL, USA, June 2023. Full Paper: Extended Version: Lightning Talk (3 mins): Full Talk (26 mins): Source Code:
HBM RowHammer [DSN Disrupt, 2023]
rowhammer
read disturbance
hbm
dram
high bandwidth
attack
Ataberk Olgun, Majd Osserian, A. Giray Yaglikci, Yahya Can Tugrul, Haocong Luo, Steve Rhyner, Behzad Salami, Juan Gomez-Luna, and Onur Mutlu, "An Experimental Analysis of RowHammer in HBM2 DRAM Chips" Proceedings of the 53nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Disrupt Track (DSN Disrupt), Porto, Portugal, June 2023. Full Paper: Full Talk (26 mins):
Ataberk Olgun, Majd Osserian, A. Giray Yaglikci, Yahya Can Tugrul, Haocong Luo, Steve Rhyner, Behzad Salami, Juan Gomez-Luna, and Onur Mutlu, "An Experimental Analysis of RowHammer in HBM2 DRAM Chips" Proceedings of the 53nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Disrupt Track (DSN Disrupt), Porto, Portugal, June 2023. Full Paper: Full Talk (26 mins):
DRAM Bender [TCAD, 2023]
dram
testing
verification
infrastructure
retention
rowhammer
real chips
Ataberk Olgun, Hasan Hassan, A Giray Yaglikci, Yahya Can Tuğrul, Lois Orosa, Haocong Luo, Minesh Patel, Oguz Ergin, Onur Mutlu, "DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023. Full Paper: Source Code:
Ataberk Olgun, Hasan Hassan, A Giray Yaglikci, Yahya Can Tuğrul, Lois Orosa, Haocong Luo, Minesh Patel, Oguz Ergin, Onur Mutlu, "DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023. Full Paper: Source Code:
RowHammer Survey [ASP-DAC, 2023]
rowhammer
survey
position
characterization
dram
mitigation
attack
DR-StRaNGe [HPCA, 2022]
end-to-end
random numbers
security
memory
dram
memory controller
F. Nisa Bostanci, Ataberk Olgun, Lois Orosa, A. Giray Yağlıkçı, Jeremie S. Kim, Hasan Hassan, Oguz Ergin, and Onur Mutlu, "DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators" Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, April 2022. Full Paper: Full Talk (24 mins):
F. Nisa Bostanci, Ataberk Olgun, Lois Orosa, A. Giray Yağlıkçı, Jeremie S. Kim, Hasan Hassan, Oguz Ergin, and Onur Mutlu, "DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators" Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, April 2022. Full Paper: Full Talk (24 mins):
DarkGates [HPCA, 2022]
power gating
package
power delivery
energy efficiency
hardware
Jawad Haj Yahya, Jeremie S. Kim, A. Giray Yağlıkçı, Jisung Park, Efraim Rotem, Yanos Sazeides, and Onur Mutlu, "DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors" Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, April 2022. Full Paper: Slides:
Jawad Haj Yahya, Jeremie S. Kim, A. Giray Yağlıkçı, Jisung Park, Efraim Rotem, Yanos Sazeides, and Onur Mutlu, "DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors" Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, April 2022. Full Paper: Slides:
QUAC-TRNG [ISCA, 2021]
random numbers
characterization
real chips
memory
dram
Ataberk Olgun, Minesh Patel, A. Giray Yağlıkçı, Haocong Luo, Jeremie S. Kim, F. Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, and Onur Mutlu, "QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips" Proceedings of the 48th International Symposium on Computer Architecture (ISCA), Virtual, June 2021. Full Paper: Full Talk (25 mins): SAFARI Live Seminar (1hr 26 mins):
Ataberk Olgun, Minesh Patel, A. Giray Yağlıkçı, Haocong Luo, Jeremie S. Kim, F. Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, and Onur Mutlu, "QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips" Proceedings of the 48th International Symposium on Computer Architecture (ISCA), Virtual, June 2021. Full Paper: Full Talk (25 mins): SAFARI Live Seminar (1hr 26 mins):
IChannels [ISCA 2021]
security
covert channels
power delivery
Jawad Haj-Yahya, Jeremie S. Kim, A. Giray Yağlıkçı, Ivan Puddu, Lois Orosa, Juan Gomez Luna, Mohammed Alser, and Onur Mutlu, "IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors" Proceedings of the 48th International Symposium on Computer Architecture (ISCA), Virtual, June 2021. Full Paper: Full Talk (21 mins):
Jawad Haj-Yahya, Jeremie S. Kim, A. Giray Yağlıkçı, Ivan Puddu, Lois Orosa, Juan Gomez Luna, Mohammed Alser, and Onur Mutlu, "IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors" Proceedings of the 48th International Symposium on Computer Architecture (ISCA), Virtual, June 2021. Full Paper: Full Talk (21 mins):
Revisiting RowHammer [ISCA, 2020]
rowhammer
characterization
real chips
memory
dram
hardware
Jeremie S. Kim, Minesh Patel, A. Giray Yağlıkçı, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, "Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020. Full Paper: Full Talk (20 mins): Lecture (55 mins):
Jeremie S. Kim, Minesh Patel, A. Giray Yağlıkçı, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, "Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020. Full Paper: Full Talk (20 mins): Lecture (55 mins):
CLR-DRAM [ISCA, 2020]
low-latency
density-performance tradeoff
memory
dram
hardware
Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, A. Giray Yağlıkçı, Lois Orosa, Jisung Park, and Onur Mutlu, "CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020. Full Paper: Full Talk (20 mins):
Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, A. Giray Yağlıkçı, Lois Orosa, Jisung Park, and Onur Mutlu, "CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020. Full Paper: Full Talk (20 mins):
SysScale [ISCA 2020]
memory
dram
hardware
Jawad Haj-Yahya, Mohammed Alser, Jeremie Kim, A. Giray Yağlıkçı, Nandita Vijaykumar, Efraim Rotem, and Onur Mutlu, "SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020. Full Paper: Full Talk (17 mins):
Jawad Haj-Yahya, Mohammed Alser, Jeremie Kim, A. Giray Yağlıkçı, Nandita Vijaykumar, Efraim Rotem, and Onur Mutlu, "SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020. Full Paper: Full Talk (17 mins):
EDEN [MICRO 2019]
approximate memory
dram latency
voltage scaling
deep neural networks
error resiliency
Skanda Koppula, Lois Orosa, A. Giray Yağlıkçı, Roknoddin Azizi, Taha Shahroodi, Konstantinos Kanellopoulos, and Onur Mutlu, "EDEN: Energy-Efficient, High-Performance Neural Network Inference Using Approximate DRAM," in Proceedings of the 52nd International Symposium on Microarchitecture (MICRO), Columbus, OH, USA, October 2019. Full Paper: Lecture (38 mins): Lightning Talk:
Skanda Koppula, Lois Orosa, A. Giray Yağlıkçı, Roknoddin Azizi, Taha Shahroodi, Konstantinos Kanellopoulos, and Onur Mutlu, "EDEN: Energy-Efficient, High-Performance Neural Network Inference Using Approximate DRAM," in Proceedings of the 52nd International Symposium on Microarchitecture (MICRO), Columbus, OH, USA, October 2019. Full Paper: Lecture (38 mins): Lightning Talk:
CROW [ISCA 2019]
memory latency
row decoder
spare rows
memory
dram
hardware
H. Hassan, M. Patel, J. S. Kim, A. Giray Yağlıkçı, N. Vijaykumar, N. Mansouri Ghiasi, S. Ghose, O. Mutlu, "CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability," in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2019. Full Paper: Full Talk: Lightning Talk:
H. Hassan, M. Patel, J. S. Kim, A. Giray Yağlıkçı, N. Vijaykumar, N. Mansouri Ghiasi, S. Ghose, O. Mutlu, "CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability," in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2019. Full Paper: Full Talk: Lightning Talk:
Vampire [SIGMETRICS 2018]
rowhammer
characterization
real chips
memory
dram
hardware
S. Ghose, A. Giray Yağlıkçı, R. Gupta, D. Lee, K. Kudrolli, W. X. Liu, H. Hassan, K. K. Chang, N. Chatterjee, A. Agrawal, M. O'Connor, and O. Mutlu, "What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study," in Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Irvine, CA, USA, June 2018. Abstract: Full Paper: POMACS Journal Version: Slides:
S. Ghose, A. Giray Yağlıkçı, R. Gupta, D. Lee, K. Kudrolli, W. X. Liu, H. Hassan, K. K. Chang, N. Chatterjee, A. Agrawal, M. O'Connor, and O. Mutlu, "What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study," in Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Irvine, CA, USA, June 2018. Abstract: Full Paper: POMACS Journal Version: Slides:
Voltron [SIGMETRICS 2017]
voltage scaling
access latency
characterization
real chips
memory
dram
hardware
K. Chang, A. Giray Yağlıkçı, S. Ghose, A. Agrawal, N. Chatterjee, A. Kashyap, D. Lee, M. O'Connor, H. Hassan, and O. Mutlu, "Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms," in Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Urbana-Champaign, IL, USA, June 2017. Abstract: Full Paper: POMACS Journal Version: Slides:
K. Chang, A. Giray Yağlıkçı, S. Ghose, A. Agrawal, N. Chatterjee, A. Kashyap, D. Lee, M. O'Connor, H. Hassan, and O. Mutlu, "Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms," in Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Urbana-Champaign, IL, USA, June 2017. Abstract: Full Paper: POMACS Journal Version: Slides:
Security Analysis of the Silver Bullet Technique for RowHammer Prevention [arXiv 2021]
rowhammer
defense
refresh
memory
dram
on-die
hardware