Abdullah Giray Yaglikci

Research and Teaching Assistant PhD Student

About Me

I am a PhD student at Safari Research Group at ETH Zürich under supervision of Prof. Onur Mutlu. I work in the field of computer architecture and particularly I focus on memory subsystem. My recent research includes the characterization of DRAM devices for energy efficient use-cases as well as improving their reliability and security.

Research Papers

Revisiting RowHammer

In this paper, we first present an experimental characterization of RowHammer on 1580 DRAM chips (408× DDR3, 652× DDR4, and 520× LPDDR4) from 300 DRAM modules (60× DDR3, 110× DDR4, and 130× LPDDR4) with RowHammer protection mechanisms disabled, spanning multiple different technology nodes from across each of the three major DRAM manufacturers. Our studies definitively show that newer DRAM chips are more vulnerable to RowHammer: as device feature size reduces, the number of activations needed to induce a RowHammer bit flip also reduces, to as few as 9.6k (4.8k to two rows each) in the most vulnerable chip we tested.

Full paper Talk Video Slides

Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, "Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.


This paper proposes Capacity-Latency-Reconfigurable DRAM (CLR-DRAM), a new DRAM architecture that enables dynamic capacity-latency trade-off at low cost. CLR-DRAM allows dynamic reconfiguration of any DRAM row to switch between two operating modes: 1) max-capacity mode, where every DRAM cell operates individually to achieve approximately the same storage density as a density-optimized commodity DRAM chip and 2) high-performance mode, where two adjacent DRAM cells in a DRAM row and their sense amplifiers are coupled to operate as a single low-latency logical cell driven by a single logical sense amplifier.

Full paper Talk Video Slides

Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, A. Giray Yaglikci, Lois Orosa, Jisung Park, and Onur Mutlu, "CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.


In this paper, we propose a new multi-domain power management technique to improve the energy efficiency of mobile SoCs. SysScale is based on three key ideas. First, SysScale introduces an accurate algorithm to predict the performance (e.g., band- width and latency) demands of the three SoC domains. Second, SysScale uses a new DVFS (dynamic voltage and frequency scaling) mechanism to distribute the SoC power to each domain according to the predicted performance demands. Third, in addition to using a global DVFS mechanism, SysScale uses domain-specialized techniques to optimize the energy efficiency of each domain at different operating points.

Full paper Talk Video Slides

Jawad Haj-Yahya, Mohammed Alser, Jeremie Kim, A. Giray Yaglikci, Nandita Vijaykumar, Efraim Rotem, and Onur Mutlu, "SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.

In this paper, we propose a methodology to exploit the DRAM error patterns under reduced voltage and reduced latency operation to improve the energy efficiency of error-resilient deep neural networks (DNNs).

Full paper

Skanda Koppula, Lois Orosa, A. Giray Yaglikci, Roknoddin Azizi, Taha Shahroodi, Konstantinos Kanellopoulos, and Onur Mutlu, "EDEN: Energy-Efficient, High-Performance Neural Network Inference Using Approximate DRAM," in Proceedings of the 52nd International Symposium on Microarchitecture (MICRO), Columbus, OH, USA, October 2019.

In this paper, we propose a flexible substrate (CROW) that enables new mechanisms for improving DRAM performance, energy efficiency, and reliability. We use this substrate to implement 1) a low-cost in-DRAM caching mechanism that lowers DRAM activation latency to frequently-accessed rows by 38% and 2) a mechanism that avoids the use of short-retention-time rows to mitigate the performance and energy overhead of DRAM refresh operations.

Lightning Talk Video ISCA19 Talk Video Full paper

Lightning Talk (pptx) Lightning Talk (pdf) ISCA19 Talk (pptx) ISCA19 Talk (pdf)

Poster (pptx) Poster (pdf)

H. Hassan, M. Patel, J. S. Kim, A. G. Yağlıkçı, N. Vijaykumar, N. Mansouri Ghiasi, S. Ghose, O. Mutlu, "CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability," in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2019.

To build an accurate model and provide insights into DRAM power consumption, we perform the first comprehensive experi- mental characterization of the power consumed by modern real- world DRAM modules. Our extensive characterization of 50 DDR3L DRAM modules from three major vendors yields four key new observations about DRAM power consumption that prior models cannot capture: (1) guard-bands in datasheets, (2) data dependency, (3) structural variation, and (4) misleading power reduction in datasheets.

Abstract Full Paper POMACS Journal Version

SIGMETRICS18 Talk (pptx) SIGMETRICS18 Talk (pdf)

S. Ghose, A. G. Yaglikci, R. Gupta, D. Lee, K. Kudrolli, W. X. Liu, H. Hassan, K. K. Chang, N. Chatterjee, A. Agrawal, M. O'Connor, and O. Mutlu, "What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study," in Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Irvine, CA, USA, June 2018.

In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by DRAM standards.

Abstract Full Paper POMACS Journal Version SIGMETRICS18 Talk (pptx) SIGMETRICS18 Talk (pdf)

K. Chang, A. G. Yaglikci, S. Ghose, A. Agrawal, N. Chatterjee, A. Kashyap, D. Lee, M. O'Connor, H. Hassan, and O. Mutlu, "Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms," in Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Urbana-Champaign, IL, USA, June 2017.

Work Experience

ETH Zürich


Scientific Assistant

March 2018 - Present

I enjoy doing cutting edge research at ETH Zürich as proudly a part of Safari Research Group. Please see my Google Scholar profile for the list of papers I participated.

My responsibilities also include teaching tasks. We teach Digital Design and Computer Architecture. We give main courses to provide a strong foundation to hundreds of students. Also, we hold seminar courses where we analyze papers that are either milestones in computer architecture research or that propose the state-of-the-art methods and groundbreaking ideas.

Intel Labs


Research Intern

September 2017 - February 2018

I interned at Intel’s Microarchitecture Research Lab for 6 months. No details are available due to NDA.

Carnegie Mellon University


Research Intern

August 2016 - August 2017

I have collaborated on two projects on DRAM characterization during my internship in CMU-SAFARI research group which are published in SIGMETRICS 2017 and 2018. In our SIGMETRICS’17 paper we characterize row activation and precharge latencies under reduced voltage operation. Our SIGMETRICS’18 paper proposes an accurate energy model for commodity DDR3 DRAM devices.

University of Notre Dame Du Lac


Research Assistant

August 2014 - August 2016

During my MSc program at University of Notre Dame, I worked on a research project that aims improving linked-data prefetching by using Software-Hardware cooperation.

TOBB University of Economics & Technology


Teaching Assistant

January 2012 - August 2014

I worked as the teaching assistant of the following courses. Digital Logic Design. Course book is Mano’s Digital Design. Lab studies were some basic implementations of logic circuits by using Verilog HDL. At the end of semester each student implements a single cycle cpu with a predefined instruction set. Computer Architecture. Fundamentals of architecture has been taught based on Hennessy & Patterson. This course have some Verilog HDL implementation assignments for particular circuits such as ALU and Register File. Microprocessors. This course focuses on Assembly language programming to clarify the fundamental concepts of computer architecture. During lab studies, Intel 8086 ASM has been used. As another example for assembly languages, KASIRGA ASM ( ASM of our own CPU - KASIRGA ) is also used in course.

Research Assistant

May 2013 - August 2014

I worked in the architecture design of an FPGA-based, OpenCL-compatible high performance accelerator design funded by ASELSAN - a Turkish Military-supported R&D company.

Internships during undergrad education

September 2008 - December 2011

Kasirga Information Systems Ltd.

September 2009 - December 2009, May 2011 - December 2011

I was employed for a particular project in which I developed an FPGA based data acquisition board for balancing machines (in partnership with TEG Electronics). Both the design and implementation of FPGA and PCB was my job. I used Verilog HDL and Xilinx tools for FPGA and Altium Designer for PCB.

Yumruk Space and Defense Industry Ltd.

May 2010 - April 2011

I worked on a military project for sensing human movement under certain circumstances. The project was supported by Turkish Ministry of Science, Industry, and Technology.

Global Aviation and Electronics Ltd

September 2008 - December 2008

I designed and implemented a GPS based tracking system.


ETH Zürich

PhD in Computer Science

2018 - Present

I enjoy doing cutting edge research at ETH Zürich as proudly a part of Safari Research Group. Please see my Google Scholar profile for the list of papers I participated.

University of Notre Dame Du Lac

MSc in Computer Science and Engineering

2014 - 2016

I worked on data prefetching/caching strategies on clusters under supervision of Prof. Sharon Hu and Prof. Michael Niemier at University of Notre Dame.

TOBB University of Economics and Technology

MSc in Computer Engineering

2011 - 2014

I worked on an FPGA based OpenCL-ready accelerator design during my Master’s thesis under supervision of Prof. Oguz Ergin and Dr. Fatih Say.

BSc in Electrical Engineering

2006 - 2011

I enjoyed my undergrad years in TOBB University, studying electrical engineering on an unofficial track of computer architecture that I pursued in the rest of my career. I also completed several projects in robotics, airplane design, autopilot design of UAVs, system design of a distributed motion sensor network, and an FPGA-based data acquisition card for balancing machines. I’ve interned with three companies for a total of 11.5 months, and worked part-time with one company during my undergrad.

More Information About Me

I’m a citizen of Turkey, residing in Zurich (Switzerland). I usually communicate with human-kind in Turkish and English, and with machine-kind in Python, C++, and Verilog HDL.

Other Projects

These are the projects that I have significantly participated in my early career (in reverse chronological order).

  • Effect of Computational Resources on Parallel Processing, Adv. Computer Architecture Course, MS
  • Is GPGPU Worth to Effort on Audio Processing Functions, Adv. Operating Systems Course, MS
  • expokent.com and cataload.com B2B Network Models, Self Initiative
  • FPGA Based Real Time Image Rotating, Embedded Systems Course, BS.
  • Autopilot Design for Unmanned Aerial Vehicle, Independent Research, BS.
  • Lagari Model Plane Design, DBF2010 Competition, AIAA


Below is a list of the people whom I have been lucky to work with.

People from academia:

People from industry: