I am a tenure-track faculty, leading the Secure and Sustainable System Scaling Lab at Helmholtz Institute Center of Information Security (CISPA). My current research aims enabling secure and sustainable system scaling as chips get denser and many users share chips. We push the boundaries of secure and sustainable system scaling via conducting research on high-performance, energy-efficient, and secure computer architectures and systems.
Join the team! We are always looking for self-motivated people. Please fill out this application form to join us.
Memory Latency, Data Retention, and Refresh
90 mins |
Video: |
Slides:
DRAM Robustness and RowHammer Lecture (Second half of the lecture)
1 hour |
Video: |
Slides:
A Deeper Look into RowHammer's Characteristics in Real Modern DRAM Chips
1 hour 50 mins |
Video: |
Slides:
Efficiently and Scalably Mitigating RowHammer in DRAM-Based Memory Systems
2 hours 4 mins |
Video: |
Slides:
Program Committee Member for HPCA, DSN, and ISCA
Program Committee Member for DRAMSec Workshop at ISCA
Submission and Web Co-Chair for DRAMSec Workshop at ISCA
Reviewer for IEEE CAL
Organization Chair for SaLWo: SAFARI Live Workshop
Artifact Evaluation Committee Member for ASPLOS and DSN
Student Assistant to PC chairs for DSN
External Program Committee Member for DSN
Reviewer for TODAES
Subreviewer for ASPLOS, DSN, ISCA, CAL, DRAMSec, TC, TCAD, and USENIX ATC
Subreviewer for HPCA, MICRO, TCAD, and USENIX ATC
Subreviewer for DSN, ISCA, MICRO, CCS, ISCAS, ISPASS, NVMW, and TCSI
Subreviewer for DSN, ISCA, MICRO, MSST, TCAD, and TED
Subreviewer for ASPLOS, HPCA, PACT, Nature Electronics, TC, and TVLSI
Subreviewer for DSN, MICRO, ISCA, and PLDI